Flash memories are high-density non-volatile memories and may be divided into data flash and code flash memories. Data flash memories are typically used for storing large data volumes and possess a large number of memory cells in each sector. Code flash memories are typically used for storing program code and require smaller portions of memory to be accessible for read, write, and erase operations. The storage capacity of flash memories can be increased by increasing the number of bits stored per cell.
Nitride programmable read-only memory (NROM) cells can store two bits per cell. FIG. 1 shows a sectional view through an NROM cell as known in the prior art. The gate G of the cell will be connected to a wordline and the two source/drain regions S/D will be connected to bitlines. Below the gate G is the so-called ONO layer which consists of a top oxide layer TO, a bottom oxide layer BO, and a nitride layer NL sandwiched between the top oxide layer TO and the bottom oxide layer BO. Electric charge can be stored in the nitride layer NL at a first location that is close to a first source/drain region S/D and at a second location that is close to the second source/drain region S/D. The channel of the NROM cell is formed between the first source/drain region S/D and the second source/drain region S/D and lies below the ONO layer in the semiconductor substrate SB.
The amount of charge stored in each location can be adjusted independently from the charge stored in the other location, so that it is possible to store a first bit B1 and a second bit B2 in a single cell. For each location, the amount of electrical charge stored determines the threshold voltage value VTH of this part of the cell. A high threshold value VTH corresponds to a programmed state and a low threshold value VTH corresponds to an erased state.
Reading the first bit B1 involves applying a gate voltage that is between the high and low threshold voltages and sensing the current flowing through the cell while applying potentials of, for example, 0 V to the first source/drain region S/D and 1.5 V to the second source/drain region S/D.
Programming the first bit B1 involves applying voltages of, for example, 4.5 V to the first source/drain S/D which is close to the first bit B1, 0 V to the second source/drain S/D, and 9 V to the gate G so that hot electrons will tunnel from the channel of the cell into the nitride layer NL.
Erasing the first bit B1 involves hot hole injection by applying, for example, a voltage of 8 V to the first source/drain S/D close to the first bit B1, floating the other source/drain S/D, and a negative voltage to the gate G.
For reading, programming and erasing the second bit B2 the voltages applied to the first and second source/drain region S/D are swapped.
For the purpose of this invention, the symbol shown in FIG. 2 is used to represent a NROM cell with a gate contact G, two source/drain contacts S/D and indicating that a first bit B1 and a second bit B2 can be stored in the cell. The source/drain contact S/D close to the first bit B1 will be called first source/drain contact while the source/drain contact S/D close to the second bit B2 will be called second source/drain contact. The same reference sign S/D is used for both the first source/drain contact and the second source/drain contact in order to indicate that the cell is symmetrical with respect to those contacts.
In order to minimize the layout area, NROM cells are frequently connected using a so-called “virtual ground array”, as illustrated in FIG. 3. A group of memory cells MC are arranged along rows and columns and connected to wordlines WL and bitlines BL. The gate contacts G of the memory cells MC arranged along rows are connected by wordlines WL. The source/drain contacts S/D of the memory cells MC arranged along columns are connected to bitlines BL, with each bitline BL being shared between two memory cells MC adjacent along rows. By sharing the bitlines BL between two cells instead of having two bitlines for each cell, the area required for the memory M can be reduced. Each first bit B1 and second bit B2 in the memory cells MC in the array M can be addressed by means of the wordline WL and the bitlines BL corresponding to the row and the column in which the memory cell MC is located.
Each time the content of memory cells MC in standard flash memories is to be altered, a block erase or sector erase followed by a programming of the sector is performed in case that the memory cells MC that are to be programmed are not already erased. This approach is a leftover from the first flash memory generation, the ETOX or floating gate flash memory, in which the memory cells shared a common substrate and source. As a consequence, whenever an erase voltage is applied to the source and/or substrate, the erase pulse is applied in parallel to all cells that share the same substrate and source terminals.
While providing compatibility, this erase and programming mechanism also has significant disadvantages for modem flash memories. As an erase operation is performed every time that the content of any of the memory cells is to be changed, the power consumption of the memory is high. Further, all cells are subjected to the erase and program cycle even if their contents need not be changed. This unnecessary cycling reduces the lifetime of the memory cell and the reliability of the memory as a whole. Further, the data throughput is reduced as at least an erase operation is performed every time data is written to the memory.